深圳市轩成微电子有限公司

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. 32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM MARCH 2016 IS42/45S83200J IS42/45S16160J 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA 54-ball BGA Parameter 32M x 8 16M x 16 Configuration 8M x 8 x 4 banks 4M x 16 x 4 banks Refresh Count Com./Ind. A1 A2 8K/64ms 8K/64ms 8K/32ms 8K/64ms 8K/64ms 8K/32ms Row Addresses A0-A12 A0-A12 Column Addresses A0-A9 A0-A8 Bank Address Pins BA0, BA1 BA0, BA1