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岳小姐 
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ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. KEY TIMING PARAMETERS Parameter -6 -7 -75E Unit Clk Cycle Time CAS Latency = 3 6 7 – ns CAS Latency = 2 10 10 7.5 ns Clk Frequency CAS Latency = 3 166 143 – Mhz CAS Latency = 2 100 100 133 Mhz Access Time from Clock CAS Latency = 3 5.4 5.4 – ns CAS Latency = 2 6.5 6.5 5.5 ns
